The present disclosure herein relates to a method of forming a semiconductor device package, and more particularly, to formation of a moulding cap of a semiconductor device package.
As the performances of electronic appliances are being improved, the operational speeds of semiconductor chips are likewise also being improved. In addition, as electronic appliances are miniaturized, compactness, slimness and lightweight trends in semiconductor packages may also increase. One of interconnection technologies for addressing these trends is the flip chip bonding technology. The flip chip bonding technology is a technology that may attach and mount each semiconductor chip obtained by cutting a wafer onto a printed circuit board without packaging the semiconductor chip. The term “flip chip” has been adopted as a chip is flipped over. A semiconductor chip may be mounted on a substrate by forming bumps on pads disposed in the upper portion of the semiconductor chip, and by connecting connection pads printed on the substrate to the bumps in a soldering manner. According to the flip chip bonding technology, as a chip can be mounted in its size on a substrate, the flip chip bonding technology is a representative chip scale package (CSP). The flip chip bonding technology is called a semiconductor mounting technology without using a lead frame, that is, a wireless semiconductor mounting technology. The flip chip bonding technology may improve electrical characteristics as a connection distance between a chip and a pad may be small, and may improves thermal characteristics as the back side of a chip may be exposed to the outside. Furthermore, the flip chip bonding technology can facilitate the attaching of solder balls using self-alignment characteristics of solder balls.
Recently, as semiconductor devices and electronic appliances including semiconductor devices grow in capacity, and are slimmed and miniaturized, various package technologies for addressing these trends are being increasingly introduced. According to one of these package technologies, various semiconductor chips can be vertically stacked to achieve high density chip stacking. This technology can integrate semiconductor chips having various functions in a smaller area than that of a typical package configured by a single semiconductor chip.
However, a package technology of stacking a plurality of semiconductor chips may be less in yield than a package technology using a single semiconductor chip. To prevent yield reduction and achieve high density chip stacking, the so-called package on package (POP) technology, which stacks a package on a package, has been suggested. As the POP technology uses semiconductor packages which passed a test, defects of final products can be reduced.
Nevertheless, there is still a need in the art for a more reliable structure in stacking semiconductor packages.